Multi-cycle symbol level error correction and memory system

Details Multi-cycle symbol level error correction and memory system Multi-cycle symbol level error correction and memory system

2006-04-11

2006-04-11

Lamarre, Guy J. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

Reexamination Certificate

active

07028248

ABSTRACT:
Symbol level multi-cycle error correction and detection coding systems are developed and deployed in computer memory architectures resulting in an increase in robustness in terms of single bus line failures having no effect on the robustness of the coding technique and capabilities. The multi-cycle symbol level error correction techniques of the present invention also provide a mechanism for reducing the pin-out requirements for memory chips and dual in-line memory modules. The resulting ECC circuitry is thus simpler and consumes less real estate.

REFERENCES:
patent: 3703705 (1972-11-01), Patel
patent: 3868632 (1975-02-01), Hong et al.
patent: 4525838 (1985-06-01), Patel
patent: 4555784 (1985-11-01), Wood
patent: 4604747 (1986-08-01), Onishi et al.
patent: 5600659 (1997-02-01), Chen

Affiliated with

Also associated with

Rating

Multi-cycle symbol level error correction and memory system does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multi-cycle symbol level error correction and memory system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multi-cycle symbol level error correction and memory system will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3567152