Self-forming metal silicide gate for CMOS devices

Details Self-forming metal silicide gate for CMOS devices Self-forming metal silicide gate for CMOS devices

2006-09-12

2006-09-12

Le, Thao P. (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S197000, C438S663000

Reexamination Certificate

active

07105440

ABSTRACT:
A process for forming a metal suicide gate in an FET device, where the suicide is self-forming (that is, formed without the need for a separate metal/silicon reaction step), and no CMP or etchback of the silicon material is required. A first layer of silicon material (polysilicon or amorphous silicon) is formed overlying the gate dielectric; a layer of metal is then formed on the first layer, and a second layer of silicon on the metal layer. A high-temperature (>700° C.) processing step, such as source/drain activation anneal, is subsequently performed; this step is effective to form a silicide layer above the gate dielectric by reaction of the metal with silicon in the first layer. A second high-temperature processing step (such as source/drain silicidation) may be performed which is effective to form a second silicide layer from silicon in the second layer. The thicknesses of the layers are such that in the high-temperature processing, substantially all of the first layer and at least a portion of the second layer are replaced by silicide material. Accordingly, a fully silicided gate structure may be produced.

REFERENCES:
patent: 6555453 (2003-04-01), Xiang et al.
patent: 6562718 (2003-05-01), Xiang et al.
patent: 2003/0207565 (2003-11-01), Tan et al.
patent: 2005/0064690 (2005-03-01), Amos et al.

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