System, method and apparatus for conserving power consumed...

Details System, method and apparatus for conserving power consumed... System, method and apparatus for conserving power consumed...

2006-04-11

2006-04-11

Lee, Thomas (Department: 2115)

Electrical computers and digital processing systems: support

Computer power control

C713S320000, C711S169000

Reexamination Certificate

active

07028196

ABSTRACT:
A processor integrated circuit has at least one processor and two or more levels of cache memory. A first power connection provides power to the processor and lower level cache, which form a first power domain. The integrated circuit has a second power connection providing power to upper level cache of the circuit, forming a second power domain. There may be additional power connections to the integrated circuit, forming additional power domains, such as periphery or memory-interface power.

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patent: 5787469 (1998-07-01), Merrell
patent: 6141762 (2000-10-01), Nicol et al.
patent: 6385710 (2002-05-01), Goldman et al.
patent: 6792551 (2004-09-01), Dai
IBM, Power Managed Second-Level Cache Control, Apr. 1, 1996, vol. 39, Issue 4, pp. 79-82.

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