Energy recycling in clock distribution networks using...

Details Energy recycling in clock distribution networks using... Energy recycling in clock distribution networks using...

2006-07-25

2006-07-25

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

07082580

ABSTRACT:
A clock distribution network for an integrated circuit includes a clock driver for generating a clock signal having a selected clock frequency, a clock net coupled to the clock driver wherein the clock net has a capacitive reactance, and an inductor coupled to the clock net wherein the inductor has an inductive reactance that is substantially equal to the capacitive reactance of the clock net at the selected clock frequency to minimize clock driver output current.

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Huo et al.; “Silicon-Based High-Q Inductors Incorporating Electroplated Copper and Low-K BCB Dielectric”;IEEE Electron Device Letters; IEEE; vol. 23, No. 9; Sep. 2002; pp. 520-522.
Lihui et al.; “High Q Multilayer Spiral Inductor on Silicon Chip for 5˜6 GHz”;IEEE Electron Device Letters; IEEE; vol. 23, No. 8; Aug. 2002; pp. 470-472.
Chi; “Salphasic Distribution of Clock Signals for Synchronous Systems”;IEEE Transactions on Computers; IEEE; vol. 43, No. 5; May 1994; pp. 597-602.

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