Method of improving the top plate electrode stress inducting...

Details Method of improving the top plate electrode stress inducting... Method of improving the top plate electrode stress inducting...

2006-07-04

2006-07-04

Zarneke, David A. (Department: 2891)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

Reexamination Certificate

active

07071509

ABSTRACT:
A method for fabricating a capacitor with overlying transistor without stress-induced voids is described. A capacitor stack is provided overlying a substrate. A stress-balancing dielectric layer is deposited overlying the stack. An anti-reflective coating (ARC) layer is deposited overlying the stress-balancing layer. The stack is patterned to form the capacitors. Gate transistors are formed overlying the capacitors wherein the stress-balancing layer prevents formation of stress-induced voids during the thermal processes involved in forming the gate transistors.

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