Self-aligned vertical gate semiconductor device

Details Self-aligned vertical gate semiconductor device Self-aligned vertical gate semiconductor device

2006-05-16

2006-05-16

Mai, Son (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S297000, C257S298000, C257S314000, C257S315000, C438S268000, C438S269000, C438S273000

Reexamination Certificate

active

07045845

ABSTRACT:
A transistor (10) is formed in a semiconductor substrate (12) whose top surface (48) is formed with a pedestal structure (24). A conductive material (40) is disposed along a side surface (28) of the pedestal structure to self-align an edge of a first conduction electrode (45) of the transistor. A dielectric spacer (55) is formed along a side surface (49) of the conductive material to self-align a contact area (56) of the first conduction electrode.

REFERENCES:
patent: 6051456 (2000-04-01), Davies et al.
patent: 6110783 (2000-08-01), Burr
patent: 6153905 (2000-11-01), Davies et al.
patent: 6197640 (2001-03-01), Davies
patent: 6268626 (2001-07-01), Jeon
patent: 06163906 (1994-06-01), None

Affiliated with

Also associated with

Rating

Self-aligned vertical gate semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Self-aligned vertical gate semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Self-aligned vertical gate semiconductor device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3556960