Semiconductor storage device

Details Semiconductor storage device Semiconductor storage device

2006-04-04

2006-04-04

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S201000

Reexamination Certificate

active

07023748

ABSTRACT:
A semiconductor storage device which can be evaluated correctly. A shift processing circuit5sequentially shifts row addresses in a line direction to reassign them in a memory cell array MSA10. A data inversion determination unit8identifies bit line pairs BL1, . . . , BL128of which the wire position switching parts CCAR10and CCAR11cross a word line specified by an input row address, according to the twisting positions and shift, to determines whether to invert the level of evaluation test data D8which is input/output to/from the bit line pairs BL1, . . . , BL128. The inversion processor4inverts the level of the evaluation test data D8which is input to and output from the bit line pairs BL1, . . . , BL128, to correctly store the evaluation test data D8of level “0”, “1” in memory cells in a storing pattern and output the data by offsetting the inversion applied at the time of storage. As a result, the semiconductor storage device can be evaluated correctly.

REFERENCES:
patent: 5140556 (1992-08-01), Cho et al.
patent: 5745420 (1998-04-01), McClure
patent: 6314011 (2001-11-01), Keeth et al.

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