Method for designing logic circuit and CAD program

Details Method for designing logic circuit and CAD program Method for designing logic circuit and CAD program

2006-09-19

2006-09-19

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07111258

ABSTRACT:
A method for designing a logic circuit and a CAD program which allow a logic circuit with desired performance to be designed in a short period of time by suppressing the elongation of a logic design period for achieving a circuit area, an operating speed, power consumption, and the like as target specifications are provided at low cost. Shorter-period and lower-cost design is accomplished by allowing a user to use a high-performance logic synthesis CAD program at no charge if he only checks circuit characteristics resulting from synthesis and collecting a fee if the user is satisfied with the resulting circuit characteristics and intends to use a gate level logic circuit. In a design phase which receives a register transfer level or operation level logic circuit and synthesizes a gate level logic circuit, desired circuit characteristics are obtainable in a short period of time at low cost.

REFERENCES:
patent: 6477683 (2002-11-01), Killian et al.
patent: 6609244 (2003-08-01), Kato et al.
patent: 2002/0138244 (2002-09-01), Meyer
patent: 2003/0200511 (2003-10-01), Nakajima

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