Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-07-18
2006-07-18
Do, Thuan (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
07080339
ABSTRACT:
Some embodiments of the invention provide a method of specifying routes in a design layout, where each route has a set of segments and each segment has a shape. The method receives a route, and for each segment of the received route, identifies n half planes that when intersected provide the shape of the segment. In some embodiments, n is an integer greater than 4. Some embodiments provide a method of generating a representation of a route formed by several adjoining polygons. For each polygon, this method (1) identifies a direction for the polygon, (2) defines a segment along the identified direction, where the segment has a starting point and an ending point, and (3) identifies more than four values that specify more than four half planes in conjunction with the starting and ending points of the segment, where the intersection of the specified half planes provides the shape of the polygon. Some embodiments provide a design layout that has several routes that are each represented by a set of segments. Each particular segment has an associated shape, which is specified by a data-storage index for the particular segment. Each particular data-storage index identifies a particular set of n values that are stored in a data storage, where, in some embodiments, n is an integer greater than 4.
REFERENCES:
patent: 5452224 (1995-09-01), Smith et al.
patent: 5508938 (1996-04-01), Wheeler
patent: 5519633 (1996-05-01), Chang et al.
patent: 5757656 (1998-05-01), Hershberger et al.
patent: 6301686 (2001-10-01), Kikuchi
patent: 6317864 (2001-11-01), Kikuchi et al.
patent: 6385758 (2002-05-01), Kikuchi et al.
patent: 6453444 (2002-09-01), Shepard
patent: 6609242 (2003-08-01), Slade
patent: 6629302 (2003-09-01), Miura et al.
patent: 6701306 (2004-03-01), Kronmiller et al.
patent: 6779167 (2004-08-01), Igarashi
patent: 6797999 (2004-09-01), Hou et al.
patent: 6813756 (2004-11-01), Igarashi et al.
patent: 6996793 (2006-02-01), Kronmiller et al.
patent: 2003/0121017 (2003-06-01), Andreev
patent: 2004/0210862 (2004-10-01), Igarashi
patent: 2004/0225983 (2004-11-01), Jacques
patent: 2004/0225990 (2004-11-01), Jacques
International Search Report, Jan. 24, 2005.
Jacques Etienne
Kronmiller Tom
Cadence Design Systems Inc.
Do Thuan
Stattler Johansen & Adeli LLP
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