Method for error detection/correction of multilevel cell...

Details Method for error detection/correction of multilevel cell... Method for error detection/correction of multilevel cell...

2006-01-24

2006-01-24

Baker, Stephen M. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

Reexamination Certificate

active

06990623

ABSTRACT:
Binary bit addresses for error detection designating the individual bits of multilevel memory cells for retaining two bits of data, respectively, are assigned so that pairs of the binary bit addresses corresponding to each of the memory cells are mutually exclusive in each digit. For each digit of the binary bit addresses, first parity codes including a parity code of data corresponding to all the binary bit addresses having “0” in the digit and a parity code of data corresponding to all the binary bit addresses having “1” in the digit are generated for both write data and read data. The presence of a memory cell storing erroneous data in both bits is detected when all the first parity codes of the read data are different from the first parity codes of the write data. Thus, the multilevel cell memory can perform reliable error detection/correction by a simple method.

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