Advanced seed layery for metallic interconnects

Details Advanced seed layery for metallic interconnects Advanced seed layery for metallic interconnects

2006-09-12

2006-09-12

Wilson, Christian D. (Department: 2891)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S625000, C438S627000, C438S628000, C438S637000, C438S641000, C438S642000, C438S643000

Reexamination Certificate

active

07105434

ABSTRACT:
One embodiment of the present invention is a method for making metallic interconnects, which method is utilized at a stage of processing a substrate having a patterned insulating layer which includes at least one opening and a field surrounding the at least one opening, the field and the at least one opening being ready for depositing one or more seed layers, which method includes steps of: (a) depositing by an ALD technique at least an initial portion of a substantially conformal seed layer on the field and inside surfaces of the at least one opening, wherein said at least one opening has a width of less than about 0.13 μm; (b) depositing by a PVD technique a substantially non-conformal seed layer over the substantially conformal seed layer, said substantially non-conformal seed layer being thicker than said substantially conformal seed layer over the field; and (c) electroplating a metallic layer over the substantially non-conformal seed layer, wherein the electroplated metallic layer consists of a material selected from a group consisting of Cu, Ag, or alloys comprising one or more of these metals.

REFERENCES:
patent: 5091209 (1992-02-01), Claverie et al.
patent: 5151168 (1992-09-01), Gilton et al.
patent: 5173442 (1992-12-01), Carey
patent: 5219787 (1993-06-01), Carey et al.
patent: 5354712 (1994-10-01), Ho et al.
patent: 5403620 (1995-04-01), Kaesz et al.
patent: 5549808 (1996-08-01), Farooq et al.
patent: 5612254 (1997-03-01), Mu et al.
patent: 5693563 (1997-12-01), Teong
patent: 5882498 (1999-03-01), Dubin et al.
patent: 5897752 (1999-04-01), Hong et al.
patent: 5913145 (1999-06-01), Lu et al.
patent: 5969422 (1999-10-01), Ting et al.
patent: 6037258 (2000-03-01), Liu et al.
patent: 6042700 (2000-03-01), Gopalraja et al.
patent: 6066892 (2000-05-01), Ding et al.
patent: 6069068 (2000-05-01), Rathore et al.
patent: 6087711 (2000-07-01), Givens
patent: 6110828 (2000-08-01), Guo et al.
patent: 6136707 (2000-10-01), Cohen
patent: 6139697 (2000-10-01), Chen et al.
patent: 6169030 (2001-01-01), Naik et al.
patent: 6174811 (2001-01-01), Ding et al.
patent: 6181012 (2001-01-01), Edelstein et al.
patent: 6184138 (2001-02-01), Ho et al.
patent: 6187670 (2001-02-01), Brown et al.
patent: 6197181 (2001-03-01), Chen
patent: 6221765 (2001-04-01), Ueno
patent: 6225221 (2001-05-01), Ho et al.
patent: 6239021 (2001-05-01), Pramanick et al.
patent: 6242349 (2001-06-01), Nogami et al.
patent: 6249055 (2001-06-01), Dubin
patent: 6251242 (2001-06-01), Fu et al.
patent: 6251528 (2001-06-01), Uzoh et al.
patent: 6251759 (2001-06-01), Guo et al.
patent: 6252304 (2001-06-01), Cole et al.
patent: 6258223 (2001-07-01), Cheung et al.
patent: 6258707 (2001-07-01), Uzoh
patent: 6274008 (2001-08-01), Gopalraja et al.
patent: 6277249 (2001-08-01), Gopalraja et al.
patent: 6281121 (2001-08-01), Brown et al.
patent: 6368954 (2002-04-01), Lopatin et al.
patent: 6374770 (2002-04-01), Lee et al.
patent: 6387800 (2002-05-01), Liu et al.
patent: 6391776 (2002-05-01), Hashim et al.
patent: 6395164 (2002-05-01), Andricacos et al.
patent: 6395642 (2002-05-01), Liu et al.
patent: 6398929 (2002-06-01), Chiang et al.
patent: 6403465 (2002-06-01), Liu et al.
patent: 6433429 (2002-08-01), Stamper
patent: 6440289 (2002-08-01), Woo et al.
patent: 6500762 (2002-12-01), Hashim et al.
patent: 6506668 (2003-01-01), Woo et al.
patent: 6515368 (2003-02-01), Lopatin et al.
patent: 6566259 (2003-05-01), Ding et al.
patent: 6582569 (2003-06-01), Chiang et al.
patent: 6605197 (2003-08-01), Ding et al.
patent: 6627542 (2003-09-01), Gandikota et al.
patent: 6686280 (2004-02-01), Shue et al.
patent: 2002/0029958 (2002-03-01), Chiang et al.
patent: 2003/0057527 (2003-03-01), Chung et al.
patent: 2003/0116427 (2003-06-01), Ding et al.
patent: 2003/0129828 (2003-07-01), Cohen
patent: 2004/0121608 (2004-06-01), Shue et al.
patent: 2004/0140196 (2004-07-01), Gopalraja et al.
patent: 2004/0147104 (2004-07-01), Lin et al.
patent: 2004/0157431 (2004-08-01), Lin et al.
patent: 2004/0188850 (2004-09-01), Lee et al.
patent: 2004/0241321 (2004-12-01), Ganguli et al.
patent: 2005/0045485 (2005-03-01), Shih et al.
patent: 2005/0110147 (2005-05-01), Wu et al.
patent: WO 0048226 (2000-08-01), None
“Biased Directional Sputtering For Barrier And Seed Layers” by S. Mizuno et al., 1999 Proc. 16thIntl VLSI Multilevel Interconn. Conf. (VMIC), Sep. 7-9, 1999, pp. 591-596.
“Cooper Barrier Bias-Temperature Stress Tests On Low-k CVD Silicon-Ocide-Based Black Diamond Films” by R. P. Mandal et al., 1999 Proc. 16thIntl VLSI Multilevel Interconn. Conf. (VMIC), Sep. 7-9, 1999, pp. 585-590.
“The Influence Of The Underlayer On The CVD Cu Nucleation” by Y. Qian et al., 1999 Proc. 16thIntl VLSI Multilevel Interconn. Conf. (VMIC), Sep. 7-9, 1999, pp. 558-562.
“Gap Filling Electro-Chemical Deposition Technology For Copper Damascene Process” by M. Zhu et al. 1999 Proc. 16thIntl VLSI Multilevel Interconn. Conf. (VMIC), Sep. 7-9, 1999, pp. 541-546.
“Study of Diffusion Barrier Properties of Ionized Metal Plasma (IMP) Deposited TaN Between Cu and SiO2” by Y. K. Lee et al., 1999 Proc. 16thIntl VLSI Multi. Inter. Conf. (VMIC), Sep. 7-9, 1999, pp. 322-324.
“Electromigration Characteristics of Damascene CVD, PVD, and Electroplated Copper Metallization” by H. S. Rathore et al., 1999 Proc. 16thIntl VLSI Multi. Inter. Conf. (VMIC), Sep. 7-9, 1999, pp. 89-92.
“Cu Dual Damascene Integration Issues” by S. Kordic et al., 1999 Proc. 16thIntl VLSI Multilevel Interconn. Conf. (VMIC), Sep. 7-9, 1999, pp. 53-62.
“Aluminum Persists as Copper Age Dawns” by A. E. Brown, Semi. Intl., Aug. 1999, pp. 58-66.
“Implications of damascene topography for electroplated copper interconnects” by M. E. Gross et al., Solid State Tech., Aug. 1999, pp. 47-52.
“Copper Electroplating Enters Mainstream Processing” by A. E. Brown, Semi. Intl., Apr. 1999, pp. 58-66.
“Barriers for copper interconnections” by C. Ryu et al., Solid State Tech., Apr. 1999, pp. 53-56.
“Copper On-Chip Interconnections” by P. C. Andricacos, The Electrochemical Society Interface, Spring 1999, pp. 31-37.
“Barrier Capabilities of Selective Chemical Vapor Deposited W Films and WSiN/WSix/W Stacked Layers Against Cu Diffusion” by M. T. Wang et al., J. Electrochemical Soc., vol. 146(2), Feb. 1999, pp. 728-731.
“Tantalum Nitride Grown by Inorganic Low Temperature Thermal Chemical Vapor Deposition” by A. E. Kaloyeros et al., J. Electrochemical Soc., vol. 146(1), Jan. 1999, pp. 170-176.
“Sputtered Cr and Reactively Sputtered CrNxServing as Barrier Layers Against Copper Diffusion” by J. C. Chuang et al., J. Electrochemical Soc., vol. 145(12), Dec. 1998, pp. 4290-4296.
“Electroplating bath control for copper interconnects” T. Taylor et al., Sol. St. Tec., Nov. 1998, pp. 47-57.
“Options for CVD of Dielectrics Include low-k Materials” by J. Baliga, Semi. Intl., Jun. 1998, pp. 139-144.
“The Challenges of the Copper CMP Clean” by D. Hymes et al., Semi. Intl, Jun. 1998, pp. 117-122.
“The Environment, Health and Safety Side of Copper Metallization” by L. Mendicino and P. T. Brown, Semi. Intl., Jun. 1998, pp. 105-110.
“Copper has enormous benefits when compared to aluminum, but its implementation requires some fundamental changes in process technologies” by P. Singer, Semi. Intl., Jun. 1998, pp. 91-98.
“Damascene copper electroplating for chip interconnections” by P. C. Andricacos et al., IBM Journal of Research & Development, vol. 42, No. 5, 1998, pp. 567-574.
“The Evolution of Interconnection Technology at IBM” by J. G. Ryan et al., IBM Journal of Research & Development, vol. 39, No. 4, 1995.
“Sputter Deposition Processes” by R. Parsons, pp. 177-208 inThin Film Processes II, Edited by J. L. Vosen and W. Kern, Academic Press (1991).
“The Catholic Arc Plasma Deposition of Thin Films” by P. C. Johnson, pp. 20

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