Electrical computers and digital processing systems: memory – Address formation – Generating prefetch – look-ahead – jump – or predictive address
Reexamination Certificate
2006-04-11
2006-04-11
Chace, Christian P. (Department: 2189)
Electrical computers and digital processing systems: memory
Address formation
Generating prefetch, look-ahead, jump, or predictive address
C711S137000, C712S207000, C712S237000
Reexamination Certificate
active
07028160
ABSTRACT:
An information processing system includes a processing unit which executes a prefetch instruction included as one of a plurality of instructions of a program in a main memory two hierarchical level caches connected to the processing unit and the main memory as arranged so that a primary cache close to the processing unit is a first level cache, and a secondary cache close to the main memory is a second level cache. The prefetch instruction, when executed, causes the processing unit to perform a prefetch operation by transferring operand data to be used in a subsequent load instruction from the main memory to the two hierarchical level data caches, prior to executing the subsequent load instruction. The prefetch instruction includes a plurality of indication bits for specifying cache levels to which the operand data is to be transferred.
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Imori Hiromitsu
Kurihara Toshihiko
Matsubara Kenji
Chace Christian P.
Hitachi , Ltd.
Mattingly ,Stanger ,Malur & Brundidge, P.C.
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