Semiconductor memory device and address conversion circuit

Details Semiconductor memory device and address conversion circuit Semiconductor memory device and address conversion circuit

2006-04-04

2006-04-04

Tran, Michael (Department: 2827)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S222000, C365S230030

Reexamination Certificate

active

07023747

ABSTRACT:
It is an object of the present invention to provide a semiconductor memory device with a suitable redundancy circuit and an address conversion circuit, wherein external addresses are allocated to both a memory cell array which needs refresh, typically DRAM and another memory cell array which does not need refresh, typically SRAM. The semiconductor memory device comprises a dynamic memory cell array11further comprising an array of a plurality of dynamic memory cells, a static memory cell array12further comprising an array of a plurality of static memory cells, a pre-decoder101for converting an external address Add into a row pre-decode signal A1or A2which corresponds to any memory cell in the dynamic memory cell array11or the static memory cell array12,a redundancy program circuit103for specifying a memory cell being to be replaced in the dynamic memory cell array11,and a second conversion means (redundancy judging circuit) for converting an external address Add, which corresponds to the memory cell specified by the redundancy program circuit103,into a row pre-decode signal A4,which corresponds to a predetermined memory cell in the static memory cell array12.

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