Method of verifying and representing hardware by...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000

Reexamination Certificate

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07028278

ABSTRACT:
A system and method for representing digital circuits and systems in multiple partitions of Boolean space, and for performing digital circuit or system validation using the multiple partitions. Decision diagrams are built for the digital circuit or system and pseudo-variables are introduced at decomposition points to reduce diagram size. Pseudo-variables remaining after decomposition are composed and partitioned to represent the digital circuit or system as multiple partitions of Boolean space. Each partition is built in a scheduled order, and is manipulable separately from other partitions.

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