Processing memory requests in a pipelined memory controller

Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing

Reexamination Certificate

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Reexamination Certificate

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07017022

ABSTRACT:
A method for processing multiple memory requests in a pipeline. Each memory request is processed in part by a plurality of stages. In a first stage, the memory request is decoded. In a second stage, the address information for the memory request is processed. In a third stage, the data for the memory request is transferred. A request buffer is used to hold each of the memory requests during the processing of each of the memory requests.

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