Semiconductor device manufacturing method and semiconductor...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S306000

Reexamination Certificate

active

07078759

ABSTRACT:
A technique is provided which makes it possible to achieve both of a reduction in contact resistance in a memory device and a reduction in contact resistance in a logic device even when oxidation is performed during formation of dielectric films of capacitors. Conductive barrier layers (82) are provided in the top ends of contact plugs (83b) electrically connected to ones of source/drain regions (59). Lower electrodes (70) of capacitors (73) are formed in contact with the conductive barrier layers (82) of the contact plugs (83b) and then dielectric films (71) and upper electrodes (72) of the capacitors (73) are sequentially formed. In the logic region, contact plugs (25) are formed in an upper layer so that they are in contact respectively with contact plugs (33) electrically connected to source/drain regions (9).

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patent: 6455370 (2002-09-01), Lane
patent: 6528366 (2003-03-01), Tu et al.
patent: 6656786 (2003-12-01), Chiang et al.
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patent: 10-150161 (1998-06-01), None
patent: 2001-267516 (2001-09-01), None
patent: 2001-284541 (2001-10-01), None
patent: 2003-7850 (2003-01-01), None

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