Verifying logic synthesizers

Details Verifying logic synthesizers Verifying logic synthesizers

2006-07-18

2006-07-18

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

07080333

ABSTRACT:
Methods and code for verifying that modifications or improvements to a synthesizer algorithm do not introduce errors. Specifically, a number or VHDL or Verilog models are chosen. Two netlists are then synthesized from each modeled circuit, once using a unmodified or trusted synthesizer, and once using the modified or improved synthesizer. For each circuit, a set of input test vectors are generated. These vectors are somewhat random in nature, but modified or generated intelligently using knowledge about the circuit to be testing. For each circuit, each netlist is simulated, generating a set of output vectors. These output vectors are compared. If the output vectors match each other for each of the circuits tested, there is a high probability that the improved or modified synthesizer is not introducing new errors into the netlist.

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