Synchronization of programmable multiplexers and demultiplexers

Details Synchronization of programmable multiplexers and demultiplexers Synchronization of programmable multiplexers and demultiplexers

2006-09-19

2006-09-19

Le, Don (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C326S046000, C713S400000, C327S042000

Reexamination Certificate

active

07109756

ABSTRACT:
Systems and methods are disclosed to provide clock and data synchronization for input/output interfaces of a programmable logic device. In accordance with one embodiment, a phase-locked loop or a delay-locked loop is employed to synchronize signals for input/output circuitry. In accordance with another embodiment, a clock divider along with an edge clock distribution scheme is employed to distribute clock and reset signals for input/output circuitry.

REFERENCES:
patent: 5675808 (1997-10-01), Gulick
patent: 6133750 (2000-10-01), Chan
patent: 6252444 (2001-06-01), Lee
patent: 6472904 (2002-10-01), Andrews
patent: 6629257 (2003-09-01), Hartwell
patent: 6744289 (2004-06-01), Nguyen
patent: 6956414 (2005-10-01), Sweet
patent: 2003/0108139 (2003-06-01), Jung
patent: 2005/0179476 (2005-08-01), Sweet
patent: 2006/0149983 (2006-07-01), Kondou

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