Semiconductor memory device with back gate potential control...

Details Semiconductor memory device with back gate potential control... Semiconductor memory device with back gate potential control...

2006-07-18

2006-07-18

Auduong, Gene N. (Department: 2827)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S189090, C365S226000

Reexamination Certificate

active

07079413

ABSTRACT:
A substrate potential setting circuits are provided which control substrate potentials in units of columns of a memory cell array at least in data writing. Upon data writing, the potential of the substrate region of memory cell transistors on a selected column is changed to reduce the data holding characteristics (static noise margin) to ensure high-speed data writing to the memory cells. Data writing is performed at high speed without impairing stability of data retention.

REFERENCES:
patent: 5900665 (1999-05-01), Tobita
patent: 6046627 (2000-04-01), Itoh et al.
patent: 6603345 (2003-08-01), Takahashi
patent: 6862227 (2005-03-01), Yamaoka et al.
patent: 09-73784 (1997-03-01), None
patent: 10-178110 (1998-06-01), None
patent: 11-213673 (1999-08-01), None
patent: P2001-339071 (2001-12-01), None
patent: P2003-60089 (2003-02-01), None
Hiroshi Kawaguchi et al., “Dynamic Leakage Cutt-Off Scheme for Low-Voltage SRAM's”, IEEE 1998 Symposium on VLSI Circuits Digest of Technical Papers, pp. 140-141.

Affiliated with

Also associated with

Rating

Semiconductor memory device with back gate potential control... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device with back gate potential control..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device with back gate potential control... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3541714