Semiconductor memory with vertical memory transistors in a...

Details Semiconductor memory with vertical memory transistors in a... Semiconductor memory with vertical memory transistors in a...

2006-07-11

2006-07-11

Tran, Minhloan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S330000, C257S329000, C257S328000, C257S316000, C257S401000

Reexamination Certificate

active

07075148

ABSTRACT:
The invention relates to a semiconductor memory having a multiplicity of memory cells, each of the memory cells having N (e.g., four) vertical memory transistors with trapping layers. Higher contact regions are formed in higher semiconductor regions extending obliquely with respect to the rows and columns of the cell array, the gate electrode generally being led to the step side areas of the higher semiconductor region. A storage density of 1-2F2per bit can thus be achieved.

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