SRAM cell with read-disturb immunity

Details SRAM cell with read-disturb immunity SRAM cell with read-disturb immunity

2006-05-16

2006-05-16

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S156000, C365S205000

Reexamination Certificate

active

07046544

ABSTRACT:
Described are small, efficient SRAM cells that are insensitive to read errors. SRAM cells in accordance with one embodiment include a pair of cross-coupled inverters extending between first and second bit nodes and a read amplifier extending from one of the first and second bit nodes to an associated bitline. During a read access to a given memory cell, the corresponding read amplifier isolates the bit nodes from the bitlines to prevent the voltage on bitline BL from disturbing data stored in the memory cell.

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V. Degalahal, “Analyzing Soft Errors in Leakage Optimized SRAM Design,” Proceedings of 16th International Conference on VLSI Design, 2003, pp. 1-11, available from Microsystems Design Laboratory, Pennsylvania State University, E-mail: {degalaha,vijay,mji}@cse.psu.edu.

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