Semiconductor nonvolatile memory cell array

Details Semiconductor nonvolatile memory cell array Semiconductor nonvolatile memory cell array

2006-09-05

2006-09-05

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S324000, C438S954000

Reexamination Certificate

active

07102192

ABSTRACT:
A semiconductor nonvolatile memory cell array includes a plurality of semiconductor nonvolatile memory cells. Each memory cell has a control electrode (30); a pair of impurity diffusion regions (21, 22) to provide first and second main electrodes; a pair of variable resistance sections (24, 26); and a pair of charge storage sections (50, 52). The array has a word line (33) electrically connected to the control electrodes of the semiconductor nonvolatile memory cells and bit lines provided perpendicular to the word line and composed of the impurity diffusion regions; and layer insulation layers (57, 58) provided between the charge storage sections and the word line.

REFERENCES:
patent: 6434053 (2002-08-01), Fujiwara
patent: 7015535 (2006-03-01), Ono et al.
patent: 5259410 (1993-10-01), None

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