Semiconductor device with isolation regions

Details Semiconductor device with isolation regions Semiconductor device with isolation regions

1994-11-08

1996-06-11

Mintel, William

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257374, 257376, 257397, 257398, H01L 2976, H01L 2994, H01L 31062, H01L 31113

Patent

active

055258247

ABSTRACT:
A multi-channel type intelligent power IC which solves the problems of parasitic transistor and increase in an area of isolation region, both of which are inherent problem in a pn junction isolation substrate. The power IC also enhances heat-radiation performance. An n type first semiconductor substrate and p type second semiconductor substrate are directly bonded, and a buried oxide film is formed in a portion of a bonding interface thereof. Subsequently, a plurality of isolation trenches are formed and the first semiconductor substrate is separated into an SOI isolation region and a pn isolation region. Logic elements are then formed in the SOI isolation region, and power elements are formed in the pn isolation region. In the case wherein two or more logic elements are hereby formed, the logic elements are isolated by isolation trenches. In the case wherein two or more power elements are formed, a parasitic current extracting portion is formed between mutual power elements.

REFERENCES:
patent: 4466011 (1984-08-01), Van Zanten
patent: 4633290 (1986-12-01), Poppert et al.
patent: 4819052 (1989-04-01), Hutter
patent: 4851366 (1989-07-01), Hunter
patent: 4980747 (1990-12-01), Hutter et al.
patent: 5045904 (1991-09-01), Kobayashi et al.
patent: 5072287 (1991-12-01), Nakagawa et al.
patent: 5111274 (1992-05-01), Tomizuka et al.

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