Electrical computers and digital data processing systems: input/ – Input/output data processing – Flow controlling
Reexamination Certificate
2006-05-23
2006-05-23
Trujillo, James K. (Department: 2116)
Electrical computers and digital data processing systems: input/
Input/output data processing
Flow controlling
C710S033000, C710S052000, C711S100000, C711S169000, C711S170000, C711S173000
Reexamination Certificate
active
07051124
ABSTRACT:
A buffer is provided with a CBW area (a randomly accessible command storage area) and an EP1area (data storage area set to FIFO), when a CBW and data are allocated as informations to be transferred through one end point EP1. When a phase switches from a USB command phase (command transport) to a data phase (data transport), the information write area is switched from the CBW area to the EP1area and OUT data transferred from the host to the end point EP1is written into the EP1area. The area switches from the CBW area to the EP1area on condition that an acknowledgment has returned to the host in the command phase. In case of a toggle missing, area switching does not occur even if ACK is returned.
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Ishida Takuya
Kamihara Yoshiyuki
Oliff & Berridg,e PLC
Trujillo James K.
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