Memory array method and system

Details Memory array method and system Memory array method and system

2006-09-05

2006-09-05

Zarabian, Amir (Department: 2827)

Static information storage and retrieval

Systems using particular element

Magnetoresistive

C365S066000, C365S173000, C365S189020, C365S189090, C365S207000, C365S209000

Reexamination Certificate

active

07102917

ABSTRACT:
An MRAM memory array includes a set of memory cell strings wherein each memory cell string has a voltage divider input, a bit-sense output, a voltage divider ground, and a bit-sense output control, a shared switched voltage line that is capable of applying a voltage to the voltage divider inputs of the memory cell strings in the set, a common bit-sense line operatively coupled to the bit-sense outputs of the memory cell strings, a bit-sense output control line that is capable of selectively connecting the bit-sense output of a memory cell string to the common bit-sense line, and a ground operatively coupled to the voltage divider grounds of the voltage divider grounds.

REFERENCES:
patent: 2005/0007816 (2005-01-01), Smith et al.
patent: 2005/0041517 (2005-02-01), Smith et al.
patent: 2005/0226071 (2005-10-01), Beers et al.

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