MONOS memory device

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Details

C257S324000, C257S411000, C257S900000

Reexamination Certificate

active

07015542

ABSTRACT:
A semiconductor device having a memory region in which a memory cell array is formed of non-volatile memory devices arranged in a matrix of plurality of rows and columns. Each of the non-volatile memory devices has: a word gate formed above a semiconductor layer with a gate insulating layer interposed; an impurity layer formed in the semiconductor layer to form a source region or a drain region; and sidewall-shaped control gates formed along both side surface of the word gate. Each of the control gates consists of a first control gate and a second control gate adjacent to each other. The first control gate and the second control gate are respectively formed on insulating layers having different thickness.

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Hayashi et al. “Twin MONOS Cell with Dual Control Gates”, 2000 Symposium on VLSI Technology Digest of Technical Papers.
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