System and method for providing adjustable read margins in a...

Details System and method for providing adjustable read margins in a... System and method for providing adjustable read margins in a...

2006-09-26

2006-09-26

Decady, Albert (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S718000, C714S724000

Reexamination Certificate

active

07114118

ABSTRACT:
A system and method for effectuating a self-timed clock (STC) loop for memory access operations wherein an Embedded Test and Repair (ETR) processor engine is utilized for optimizing an access margin value. Upon compiling a semiconductor memory instance based on its configuration data, a default access margin value is passed to a wrapper interface associated with the memory instance. In one implementation, an adjusted access margin value is determined by an optimization algorithm operable to be executed on the ETR processor engine, which adjusted access margin value is used for generating the STC signal with a particular time setting that is optimized for a memory instance of a given size.

REFERENCES:
patent: 5883844 (1999-03-01), So
patent: 6477370 (2002-11-01), Sigler et al.
patent: 6687183 (2004-02-01), Peterson et al.
patent: 6792576 (2004-09-01), Chidlovskii
patent: 2003/0120457 (2003-06-01), Singh et al.

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