Method for designing semiconductor circuit device, utilizing...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000

Reexamination Certificate

active

07103866

ABSTRACT:
To design a chip having a plurality of circuit areas driven by different power supplies, a boundary cell to be inserted on the boundary between the circuit areas is prepared. After creating a logic circuit netlist with a design tool, the boundary cell is inserted on the boundary. The boundary cell is connected on a signal transmission path between the circuit areas. A circuit for suppressing shoot-through current or leakage current is used as the boundary circuit. By preparing the boundary cell in a cell library, chip design is facilitated.

REFERENCES:
patent: 5610791 (1997-03-01), Voldman
patent: 6140864 (2000-10-01), Hirata et al.
patent: 6308312 (2001-10-01), Houston
patent: 6603219 (2003-08-01), Toyama et al.
patent: 6941534 (2005-09-01), Fukasawa
patent: 2001-148625 (2001-05-01), None

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