Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-04-04
2006-04-04
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07024654
ABSTRACT:
A system is provided for programming a configurable semiconductor device. The system includes a programmable controlling device, a programmable computing device, a communication link, a configurable hardware device, a design tool with first computer program code, and second computer program code. The configurable hardware device has memory with a plurality of memory locations and coupled with the programmable controlling device via the communication link. The design tool includes first computer program code embodied in a programmable computing device. The second computer program code is generated at least in part by the first computer program code and is embodied in the programmable controlling device for: a) applying configuration data to selected memory locations within the configurable hardware device to configure the configurable hardware device; b) determining a location of a subset of at least one of (i) the programmable memory locations in the configurable hardware device and (ii) the configuration data to be modified; and c) determining a new data value to be applied to the subset of at least one of (i) the memory locations in the configurable hardware device and (ii) the configuration data. The design tool provides at least one of configuration data, address data, and a data value algorithm usable in performing at least one of a), b), and c). A method is also provided.
REFERENCES:
patent: 5493672 (1996-02-01), Lau et al.
patent: 5583450 (1996-12-01), Trimberger et al.
patent: 5598344 (1997-01-01), Dangelo et al.
patent: 5737235 (1998-04-01), Kean et al.
patent: 5745734 (1998-04-01), Craft et al.
patent: 5794062 (1998-08-01), Baxter
patent: 5838165 (1998-11-01), Chatter
patent: 5841967 (1998-11-01), Sample et al.
patent: 5931959 (1999-08-01), Kwiat
patent: 5966534 (1999-10-01), Cooke et al.
patent: 6006022 (1999-12-01), Rhim et al.
patent: 6041400 (2000-03-01), Ozcelik et al.
patent: 6053951 (2000-04-01), McDonald et al.
patent: 6058469 (2000-05-01), Baxter
patent: 6091263 (2000-07-01), New et al.
patent: 6092174 (2000-07-01), Roussakov
patent: 6150839 (2000-11-01), New et al.
patent: 6182206 (2001-01-01), Baxter
patent: 6230307 (2001-05-01), Davis et al.
patent: 6255849 (2001-07-01), Mohan
patent: 6260139 (2001-07-01), Alfke
patent: 6272669 (2001-08-01), Anderson et al.
patent: 6288566 (2001-09-01), Hanrahan et al.
patent: 6304101 (2001-10-01), Nishihara
patent: 6308253 (2001-10-01), Gadre et al.
patent: 6308311 (2001-10-01), Carmichael et al.
patent: 6314553 (2001-11-01), Stevens et al.
patent: 6324676 (2001-11-01), Burnham et al.
patent: 6326806 (2001-12-01), Fallside et al.
patent: 6327253 (2001-12-01), Frink
patent: 6339827 (2002-01-01), Stokes et al.
patent: 6346824 (2002-02-01), New
patent: 6356862 (2002-03-01), Bailey
patent: 6357037 (2002-03-01), Burnham et al.
patent: 6438737 (2002-08-01), Morelli et al.
patent: 6584601 (2003-06-01), Kodosky et al.
patent: 2001/0025231 (2001-09-01), Kodosky et al.
patent: WO95/32478 (1995-11-01), None
“An FPGA/FPAA-Based Rapid Prototyping Environment for Mixed Signal Systems”, by Sree Ganesan and Ranga Vemuri, undated, Lab for Digital Design Environments; U of Cincinnati.
“Configuration Code Generation and Optimizations for Heterogeneous Reconfigurable DSPS”, pp. 169-180 by Suet-Fei Li, et al., I Signal Processing Systems, 1999, SIPS 99, 1999 IEEE Workshop, Taipei, Taiwan, Oct. 20-22, 1999.
Dynamically Reconfigurable Analog/Digital Hardware—Implementation Using FPGA and FPAA Technologies, by Cornel Reiser, et al., International Winter Conference of the Society for Computer Simulation, Jan. 17-19, 1999.
“JPG—A Partial Bistream Generation Tool to Support Partial Rconfiguration in Virtex FPGAs”, by Anup Kumar Raghavan, et al., Parallel and Distributed Processing Symposium, Proceedings International, IPDPS 2002, Apr. 15-19, 2002.
“Design Methodology of a Low-Energy Reconfigurable Single-Chip DSP System”, by Marlene Wan, et al., pp. 47-61, Journal of VLSI Signal Processing Systems for Signal Image and Video Technology, vol. 28 No. 1/2, May 2001.
Anderson Howard C.
Bersch Danny Austin
Giles Troy Franklin
Macbeth Ian Craig
Nottingham Brian Eugene
Anadigm, Inc.
Levin Naum
Smith Matthew
Wells St. John P.S.
LandOfFree
System and method for configuring analog elements in a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System and method for configuring analog elements in a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for configuring analog elements in a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3528810