Microprocessor including cache memory supporting multiple...

Details Microprocessor including cache memory supporting multiple... Microprocessor including cache memory supporting multiple...

2006-07-04

2006-07-04

Padmanabhan, Mano (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S003000, C711S144000, C711S106000, C711S147000, C711S131000, C711S140000, C711S150000, C711S154000, C711S170000

Reexamination Certificate

active

07073026

ABSTRACT:
A microprocessor including a level two cache memory which supports multiple accesses per cycle. The microprocessor includes an execution unit coupled to a cache memory subsystem which includes a cache memory coupled to a plurality of buses. The cache memory includes a plurality of independently accessible storage blocks. The buses may be coupled to convey a plurality of cache access requests to each of the storage blocks. In response to the plurality of cache access requests being conveyed on the plurality of cache buses, different ones of the storage blocks are concurrently accessible.

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