Semiconductor memory device having column address path...

Static information storage and retrieval – Read/write circuit – Signals

Reexamination Certificate

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C365S233100, C365S230080

Reexamination Certificate

active

07102939

ABSTRACT:
There is provided a semiconductor memory device capable of reducing power consumption by preventing unnecessary operations of an AL flip-flop delay unit and a CL flip-flop delay unit. The semiconductor memory device includes an internal column address generation means for receiving an external column address and generating an internal column address; a delay means for delaying the internal column address for a predetermined time corresponding to a preset latency; and a driving control means for driving the delay means for the predetermined time corresponding to the preset latency.

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