Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2006-01-24
2006-01-24
Portka, Gary (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S133000, C711S118000, C711S159000, C712S237000
Reexamination Certificate
active
06990558
ABSTRACT:
An apparatus in a microprocessor for selectively retiring a prefetched cache line is disclosed. In a first embodiment, a first count of the number of accesses to the prefetched cache line and N second counts of the number of accesses to N lines of a replacement candidate set of the cache selected by the prefetched cache line address are maintained. When another prefetch is requested, if the first count is greater than the smaller of the N second counts, the candidate prefetched cache line is retired into the cache; otherwise the prefetched cache line is discarded. In a second embodiment, a count of accesses to the replacement candidate line is maintained. When another prefetch is requested, if the count is greater than a programmable threshold value, the candidate prefetched cache line is retired into the cache; otherwise the prefetched cache line is discarded.
REFERENCES:
patent: 6138213 (2000-10-01), McMinn
patent: 6523093 (2003-02-01), Bogin et al.
patent: 2002/0129205 (2002-09-01), Anderson et al.
Henry Glenn
Hooker Rodney
Davis E. Alan
Huffman James W.
IP-First LLC
Song Jasmine
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