Memory device with common row interface

Details Memory device with common row interface Memory device with common row interface

Filed on

2006-01-03

Date issued

2006-01-03

Examiner

Hoang, Huan (Department: 2827)

Patent Class

Static information storage and retrieval

SubClass

Read/write circuit

SubSubClass

Bad bit

Other Related Categories

C365S230030, C365S189070

Type

Reexamination Certificate

Status

active

Patent number

06982911

Description

ABSTRACT:
One embodiment of the present invention provides a semiconductor memory receiving an external address including an array address and a row address. The semiconductor memory includes a memory bank having N arrays, each array having an array address and a plurality of primary rows of memory cells and a plurality of redundant rows of memory cells, a redundancy block, and N local row control blocks. The redundancy block provides a match signal having an active state when the external address matches one of a plurality of defective addresses, provides a redundant row address when the match signal has the active state, and provides a redirected array address comprising a redundant array address when the match signal has the active state and otherwise comprising the external array address. Each of the N local row control blocks is associated with a different one of the N arrays, wherein the local row control block associated with the array whose address matches the redirected array address opens a redundant row of memory cells for access based on the redundant row address when the match signal has the first state, and otherwise opens a normal row of memory cells for access based on the external row address.

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Copy of PCT International Search Report for International Application No. PCT/EP2005/001896 (4 pgs.).

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