Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2006-01-10
2006-01-10
Thompson, Craig A. (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S761000, C257S758000, C257S770000, C438S618000, C438S622000
Reexamination Certificate
active
06984891
ABSTRACT:
A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with aluminum wires. Yet, aluminum wires have greater electrical resistance and are less reliable than copper wires. Unfortunately, current techniques for making copper wires are time-consuming and inefficient. Accordingly, the invention provides a method of making wires or interconnects from copper or other metals. One embodiment entails forming a first diffusion barrier inside a trench using ionized-magnetron sputtering for better conformal coating of the trench, and a second diffusion barrier outside the trench using jet-vapor deposition. The jet-vapor deposition has an acute angle of incidence which prevents deposition within the trench and thus eliminates conventional etching steps that would otherwise be required to leave the trench free of this material. After formation of the two diffusion barriers, the trench is filled with metal and annealed.
REFERENCES:
patent: 2842438 (1958-07-01), Saarivirta et al.
patent: 3954570 (1976-05-01), Shirk et al.
patent: 4386116 (1983-05-01), Nair et al.
patent: 4423547 (1984-01-01), Farrar et al.
patent: 4574095 (1986-03-01), Baum et al.
patent: 4762728 (1988-08-01), Keyser et al.
patent: 4788082 (1988-11-01), Schmitt
patent: 4931410 (1990-06-01), Tokunaga et al.
patent: 4962058 (1990-10-01), Cronin et al.
patent: 4996584 (1991-02-01), Young et al.
patent: 5019531 (1991-05-01), Awaya et al.
patent: 5100499 (1992-03-01), Douglas
patent: 5130274 (1992-07-01), Harper et al.
patent: 5149615 (1992-09-01), Chakravorty et al.
patent: 5158986 (1992-10-01), Cha et al.
patent: 5173442 (1992-12-01), Carey
patent: 5240878 (1993-08-01), Fitzsimmons et al.
patent: 5243222 (1993-09-01), Harper et al.
patent: 5256205 (1993-10-01), Schmitt, III et al.
patent: 5334356 (1994-08-01), Baldwin et al.
patent: 5354712 (1994-10-01), Ho et al.
patent: 5426330 (1995-06-01), Joshi et al.
patent: 5442237 (1995-08-01), Hughes et al.
patent: 5470789 (1995-11-01), Misawa
patent: 5470801 (1995-11-01), Kapoor et al.
patent: 5476817 (1995-12-01), Numata
patent: 5506449 (1996-04-01), Nakano et al.
patent: 5529956 (1996-06-01), Morishita
patent: 5538922 (1996-07-01), Cooper et al.
patent: 5539060 (1996-07-01), Tsunogae et al.
patent: 5595937 (1997-01-01), Mikagi
patent: 5625232 (1997-04-01), Numata et al.
patent: 5635253 (1997-06-01), Canaperi et al.
patent: 5662788 (1997-09-01), Sandhu et al.
patent: 5674787 (1997-10-01), Zhao et al.
patent: 5675187 (1997-10-01), Numata et al.
patent: 5679608 (1997-10-01), Cheung et al.
patent: 5681441 (1997-10-01), Svendsen et al.
patent: 5695810 (1997-12-01), Dubin et al.
patent: 5739579 (1998-04-01), Chiang et al.
patent: 5780358 (1998-07-01), Zhou
patent: 5785570 (1998-07-01), Bruni
patent: 5792522 (1998-08-01), Jin et al.
patent: 5801098 (1998-09-01), Fiordalice et al.
patent: 5889295 (1999-03-01), Rennie et al.
patent: 5891797 (1999-04-01), Farrar
patent: 5891804 (1999-04-01), Havemann et al.
patent: 5893752 (1999-04-01), Zhang et al.
patent: 5897370 (1999-04-01), Joshi et al.
patent: 5911113 (1999-06-01), Yao et al.
patent: 5913147 (1999-06-01), Dubin et al.
patent: 5932928 (1999-08-01), Clampitt
patent: 5933758 (1999-08-01), Jain
patent: 5968333 (1999-10-01), Nogami et al.
patent: 5969422 (1999-10-01), Ting et al.
patent: 5972804 (1999-10-01), Tobin et al.
patent: 5976710 (1999-11-01), Sachdev et al.
patent: 5981350 (1999-11-01), Geusic et al.
patent: 5985759 (1999-11-01), Kim et al.
patent: 5994777 (1999-11-01), Farrar
patent: 6001730 (1999-12-01), Farkas et al.
patent: 6008117 (1999-12-01), Hong et al.
patent: 6030877 (2000-02-01), Lee et al.
patent: 6054172 (2000-04-01), Robinson et al.
patent: 6069068 (2000-05-01), Rathore et al.
patent: 6168704 (2001-01-01), Brown et al.
patent: 405267643 (1993-10-01), None
patent: 405267643 (1993-10-01), None
patent: 07-321111 (1995-08-01), None
Hirao, “A Novle Copper Reflow Using Dual Wetting Layers”, 1997 Symposiom on VLSI Technology Digest of Technical Papers), pp. 57-58.
Chakravorty, K.K., et al., “High-Density Interconnection Using Photosensitive Polyimide and Electroplated Copper Conductor Lines”,IEEE Transactions on Components, Hybrids, and Manufacturing Technology, 13(1), pp. 200-206, (Mar. 1990).
In: Kirk-Othmer Concise Encyclopedia of Chemical Technology, Grayson, M., (ed.), John Wiley & Sons, Inc., New York, NY, p. 433-435, 926-938, (1985).
In: Metals Handbook, 8th Edition, vol. 8, ASM Handbook Committee, (eds.), American Society for Metals, Materials Park, OH, p. 300-302.
In: Metals Handbook, Ninth Edition, vol. 2, Properties and Selection: Nonferrous Alloys and Pure Metals, ASM Handbook Committee, (eds.), American Society for Metals, Metals Park, OH, 157, 395, (1989).
“Brooks Model 5964 High Performance Metal Seal Mass Flow Controller (Introduced in 1991)”,Brooks Instrument, http://www.frco.com/brooks/semiconductor/productsli.html, 1 page, (1991).
Abe, K., et al., “Sub-half Micron Copper Interconnects Using Reflow of Sputtered Copper Films”,VLSI Multilevel Interconnection Conference, 308-311, (Jun. 25-27, 1995).
Andricacos, P.C., “Copper On-Chip Interconnections”,The Electrochemical Society Interface, pp. 32-37, (1999).
Anonymous, “Formation of Conductors at Variable Depths—Using Differential Photomask, Projecting Images into Insulator by Reactive Ion Etching, Selectively Filling Images with Conductor”,Research Disclosure, Disclosure No. RD 291015, Abstract, 1 p., (Jul. 10, 1988).
Anonymous, “Improved Metallurgy for Wiring Very Large Scale Integrated Circuits”,International Technology Disclosures, 4, Abstract, 1 page, (1986).
Bae, S., et al., “Low-Temperature Deposition Pathways to Silicon Nitride, Amorphous Silicon, Polycrystalline Silicon, and n type Amorphous Silicon Films Using a High Density Plasma System”,IEEE Conference Records—Abstracts, International Conference on Plasma Science, p. 315, (1997).
Bai, G., et al., “Copper Interconnection Deposition Techniques and Integration”,1996 Symposium on VLSI Technology, Digest of Technical Papers, 48-49, (1996).
Bernier, M., et al., “Laser processing of palladium for selective electroless copper plating”,SPIE, 2045, pp. 330-337, (1994).
Bhansali, S., et al., “A novel technique for fabrication of metallic structures on polymide by selective electroless copper plating using ion implantation”,Thin Solid Films, 270, pp. 489-492, (1995).
Bhansali, S., et al., “Selective electroless copper plating on silicon seeded by copper ion implantation”,Thin Solid Films, 253, pp. 391-394, (1994).
Braud, E., et al., “Ultra Thin Diffusion Barriers for Cu Interconnections at The Gigabit Generation and Beyond”,VMIC Conference Proceedings, pp. 174-179, (1996).
Cabrera, A.L., et al., “Oxidation protection for a variety of transition metals and copper via surface silicides formed with silane containing atmospheres”,J. Mater. Res., 6(1), pp. 71-79, (1991).
Craig, J.D., “Polymide Coatings”,In: Packaging, Electronic Materials Handbook, vol. 1, ASM International Handbook Committee (eds.), ASM International, Materials Park, OH, 767-772, (1989).
de Felipe, T.S., et al., “Electrical Stability and Microstructural Evolution in Thin Films of High Conductivity Copper Alloys”,IEEE, pp. 293-295, (1999).
Ding, et al., “Copper Barrier, Seed Layer and Planerization Technologies”,VMIC Conference Proceedings, pp. 87-92, (1997).
Dubin, V.M., et al., “Selective and Blanket Electroless Copper Deposition for Ultralarge Scale Integration”,J. Electrochem. Soc., 144(3), pp. 898-908, (1997).
Dushman, S., et al.,Scientific Foundations of Vacuum Technique, 2nd Edition, John Wiley and Sons, 1-806, (1962).
Edelstein, D., et al., “Full Copper Wiring in a Sub-0.25 micrometer CMOS ULSI Technology”,IEDM, pp. 773-776, (1997).
Eldridge, J.M., “New Approaches for Investigating Corrosion in
Ahn Kie Y.
Forbes Leonard
Mitchell James M.
Schwegman, Lunberg, Woessner & Kluth, P.A.
Thompson Craig A.
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