Refresh-free dynamic semiconductor memory device

Details Refresh-free dynamic semiconductor memory device Refresh-free dynamic semiconductor memory device

2005-08-02

2005-08-02

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S230060, C365S230030, C365S189050, C365S227000

Reexamination Certificate

active

06925022

ABSTRACT:
In a data holding mode, data storage in a one bit/one cell scheme in a normal operating mode are rearranged into data storage in a twin-cell mode in which data are stored in a one bit/two cell scheme. In the twin-cell mode, two sub word lines are simultaneously driven into a selected state, and storage data of memory cells are read out on both of bit lines in a pair, to perform a sense operation. Thus, the read-out voltage can be increased to improve the data retention characteristics for lengthening a refresh interval, resulting in a reduced power consumption in the data holding mode.

REFERENCES:
patent: 5661678 (1997-08-01), Yoshida et al.
patent: 6272054 (2001-08-01), Barth, Jr. et al.
patent: 6344990 (2002-02-01), Matsumiya et al.
patent: 6449204 (2002-09-01), Arimoto et al.
patent: 1502334 (1978-03-01), None
patent: 55-157194 (1980-12-01), None
patent: 61-34790 (1986-02-01), None
patent: 04-098679 (1992-03-01), None
patent: 8-222706 (1996-08-01), None

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