Memory device comprising hysteretic capacitance means

Details Memory device comprising hysteretic capacitance means Memory device comprising hysteretic capacitance means

2005-12-13

2005-12-13

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S149000, C365S189070

Reexamination Certificate

active

06975530

ABSTRACT:
A memory device capable of suppressing reduction of a read margin resulting from fluctuation of a reference potential while reducing the area of a memory cell array is obtained. This memory device comprises hysteretic capacitance device and a read circuit applying a bias voltage to the capacitance means in different directions in a first time and a second time of data reading respectively for defining read data by comparing first read data and second read data with each other.

REFERENCES:
patent: 5086412 (1992-02-01), Jaffe et al.
patent: 6788563 (2004-09-01), Thompson et al.
patent: 02-154388 (1990-06-01), None
Junichi Yamada, Tohru Miwa, Hiroki Koike, and Hideo Toyoshima, A Self-Reference Read Scheme for a 1T/1C FeRAM, 1998 IEEE.
“Ferroelectric Thin Film Memory,” Seventh Section “Liability and Assessment Technology of Ferroelectric Memory,” I. Switching Fatigue Characteristic, Jun. 30, 1994.
Second Section, MRAM, “Now in production and coming in 2004, 256 M bit,” Nikkei Electronics, Feb. 12, 2001 (No. 789), pp. 164-171.

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