Placement method for integrated circuit design using...

Details Placement method for integrated circuit design using... Placement method for integrated circuit design using...

Filed on

2005-02-01

Date issued

2005-02-01

Examiner

Siek, Vuthe (Department: 2825)

Patent Class

Computer-aided design and analysis of circuits and semiconductor

SubClass

Nanotechnology related integrated circuit design

Other Related Categories

C716S030000, C716S030000, C716S030000, C716S030000, C716S030000

Type

Reexamination Certificate

Status

active

Patent number

06851099

Description

ABSTRACT:
The present invention, generally speaking, provides a placement method for the physical design of integrated circuits in which natural topological feature clusters (topo-clusters) are discovered and exploited during the placement process. Initial placement and placement refinement may be performed hierarchically using topocluster trees. A topocluster tree may be used to drive initial placement. An iterative placement refinement process then follows, using a technique referred to herein as Geometrically-Bounded FM (GBFM). In GBFM, FM is applied on a local basis to windows encompassing some number of bins. From iteration to iteration, windows may shift position and vary in size. When a region bounded by a window meets a specified cost threshold in terms of a specified cost function, that region does not participate. The cost function takes account of actual physical metrics-delay, area, congestion, power, etc. During placement refinement using GBFM, cluster size is adjusted iteratively from large to small as determined by horizontal cuts within the topocluster tree. GBFM occurs in the context of recursive quadrisection. Hence, after GBFM has been completed, a further quadrisection step is performed in which each bin is divided into four bins, with a quarter of the gates of the original bin being placed in the center of each of the resulting bins. GBFM then follows, and the cycle repeats until each bin contains a fairly small number of gates. Topocluster trees may also be used for quadrisection. Following the foregoing global placement process, the circuit is then ready for detailed placement in which cells are assigned to placement rows.

REFERENCES:
patent: 5276789 (1994-01-01), Besaw et al.
patent: 5491641 (1996-02-01), Scepanovic et al.
patent: 5495419 (1996-02-01), Rostoker et al.
patent: 5526517 (1996-06-01), Jones et al.
patent: 5557533 (1996-09-01), Koford et al.
patent: 5636125 (1997-06-01), Rostoker et al.
patent: 5661663 (1997-08-01), Scepanovic et al.
patent: 5682321 (1997-10-01), Ding et al.
patent: 5682322 (1997-10-01), Boyle et al.
patent: 5699265 (1997-12-01), Scepanovic et al.
patent: 5712793 (1998-01-01), Scepanovic et al.
patent: 5909376 (1999-06-01), Scepanovic et al.
patent: 6099580 (2000-08-01), Boyle et al.
patent: 6145117 (2000-11-01), Eng
patent: 6286128 (2001-09-01), Pileggi et al.
Kim et al, “An Improved Hierarchical Placement Technique Using Clustering & Region Refinement,” IEEE, 1996, pp. 393-396.*
Gupta et al, “A Hierarchical Technique for Minimum-Width Layout of Two-Dimensional CMOS Cells, ” IEEE, 1996, pp. 15-20.*
Fiduccia et al., “A Linear-Time Heuristic for Improving Network Partitions”,IEEE 19thDesign Automation Conference, pp. 175-181 (1982).
Huang et al., “Partitioning-Based Standard-Cell Global Placement With an Exact Objective”,International Symposium on Physical Design, pp. 18-25, ACM (1997).
Kernighan et al., “An Efficient Heuristic Procedure for Partitioning Graphs”,Bell System Technical Journal, 49:291-307 (1970).
Kleinhans et al., “GORDIAN: VLSI Placement by Quadratic Programming and Slicing Optimization”,IEEE Transactions on Computer-Aided Design, 10(3):356-365 (1991).
Sarrafzadeh et al., “NRG: Global and Detailed Placement”,IEEE International Conference on Computer-Aided Design, pp. 532-537 (1997).
Suaris et al., “Quadrisection: A New Approach to Standard Cell Layout”,IEEE International Conference on Computer-Aided Design, pp. 474-477 (1987).

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