Shift register control of a circular elasticity buffer

Details Shift register control of a circular elasticity buffer Shift register control of a circular elasticity buffer

2005-12-20

2005-12-20

Sparks, Donald (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S100000, C711S109000, C710S052000, C710S053000, C710S054000, C710S056000

Reexamination Certificate

active

06978344

ABSTRACT:
A shift register is provided to monitor the difference between the read and write pulses to an elasticity buffer. The shift register essentially eliminates the need for any math functions in the elasticity buffer management logic. The shift register is as wide as the elasticity buffer is deep. In other words, for every word in the elasticity buffer, the shift register has a corresponding bit. Each time a word is written into the elasticity buffer without a simultaneous corresponding read, a value of “1” is shifted from a first end into the shift register, indicating that a space has been taken in the elasticity buffer. For every word read out of the elasticity buffer without a simultaneous corresponding write, a value of “0” (zero) is shifted from a second end of the shift register, indicating that one more space is available. The elasticity buffer management logic need only monitor the shift register value to determine whether the elasticity buffer is nearly empty or nearly full, and if fill words need to be inserted or deleted.

REFERENCES:
patent: 5323426 (1994-06-01), James et al.
patent: 5771356 (1998-06-01), Leger et al.
patent: 6044416 (2000-03-01), Hasan
patent: 6408349 (2002-06-01), Castellano
patent: 6529971 (2003-03-01), Thiesfeld
patent: 6696854 (2004-02-01), Momtaz et al.
patent: 2002/0174273 (2002-11-01), Castellano

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