Viterbi decoder using restructured trellis

Details Viterbi decoder using restructured trellis Viterbi decoder using restructured trellis

2005-06-21

2005-06-21

Dildine, R. Stephen (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S786000, C714S792000

Reexamination Certificate

active

06910177

ABSTRACT:
Viterbi decoding is implemented using an asymmetrical trellis70having an A-trellis72and a B-trellis74. The trellis70is designed for efficient implementation on a processing device40with arithmetic units42having multi-field arithmetic and logic capabilities By concurrently processing multiple path metrics in separate fields, a highly efficient decoder may be implemented in a software-controlled device.

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