Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2005-12-20

2005-12-20

Tran, Michael (Department: 2827)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S225700

Reexamination Certificate

active

06977851

ABSTRACT:
A semiconductor memory device has a redundant memory cell array having redundant memory cells arranged in redundant rows and columns and has first and second fuse blocks. The first fuse block has first fuses for corresponding to an address of a row address signal. The second fuse block has second fuses for corresponding to a column address signal. The first fuse block stores an address of a defective row of the memory cell and the second fuse block stores an address of a defective column of the memory cell. Furthermore, the semiconductor memory device has an address matching detector connected with the first and second fuses. The address matching detector checks consistency of the address of the row or column address signal with the address of the defective row or column.

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patent: 6704228 (2004-03-01), Jang et al.
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patent: 6728158 (2004-04-01), Takahashi et al.
patent: 07-211779 (1995-08-01), None
patent: 7-211779 (1995-08-01), None
patent: 2002-15593 (2002-01-01), None

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