Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-08-30
2005-08-30
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06938234
ABSTRACT:
Some embodiments of the invention provide a method of routing nets in a region of a design layout. The region contains a plurality of nets and has multiple interconnect layers. The method identifies routes for a set of nets in the region, where some of the routes utilize vias to traverse multiple interconnect layers. The method then moves at least one via to improve the routing.
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Caldwell Andrew
Jacques Etienne
Teig Steven
Cadence Design Systems Inc.
Siek Vuthe
Stattler, Johansen and Adeli LLP
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