Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2005-12-27
2005-12-27
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S128000
Reexamination Certificate
active
06981096
ABSTRACT:
Architectures, methods and systems are presented which combine a multiple of directories (e. g. L1and L2directory) into a single directory, while still allowing the individual levels to use their own organization which is best for overall performance. This integration is performed without compromising the organization at each level. With some small additions to the L2directory, it is used simultaneously to perform both the L1and L2directory functions. Additionally, the same organizational structure allows the L2array to serve both as a traditional L1and simultaneous L2array. In one aspect of the present invention an architecture is provided for a first and second level memory hierarchy, or cache, including a first data storage array for the first level memory hierarchy; a second data storage array for the second level memory hierarchy, a single address translation directory combining the directories for the first and second level memory hierarchy into a single directory satisfying the organization requirements of both the first and second level memory hierarchy. Also provided is a system having three level memory hierarchy comprising: a single combined directory used to serve each of three separate storage arrays. Each of the storage arrays serves a respective level of the three level memory hierarchy wherein the organization of the various levels is not compromised by the use of the single combined directory.
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patent: 6065101 (2000-05-01), Gilda
Matick Richard E.
Schuster Stanley Everett
Beck Thomas A.
Herzberg Louis
Kim Matthew
Vital Pierre M.
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