Synchronous flash memory with concurrent write and read...

Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area

Reexamination Certificate

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Details

C711S103000, C711S005000, C710S052000, C710S053000, C710S061000, C365S185330, C365S189050, C365S189110

Reexamination Certificate

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06851026

ABSTRACT:
A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in addressable blocks. Data communication connections are used for bi-directional data communication with an external device(s), such as a processor or other memory controller. A write latch is coupled between the data buffer and the memory array to latch data provided on the data communication connections. The memory can write data to one location, such as a memory array block, while data is read from a second location, such as a second memory array block. The write and read operations are performed on a common addressable row of the array blocks.

REFERENCES:
patent: 5041886 (1991-08-01), Lee
patent: 5537354 (1996-07-01), Mochizuki et al.
patent: 5600605 (1997-02-01), Schaefer
patent: 5602781 (1997-02-01), Isobe
patent: 5657292 (1997-08-01), McClure
patent: 5666321 (1997-09-01), Schaefer
patent: 5666322 (1997-09-01), Conkle
patent: 5732017 (1998-03-01), Schumann et al.
patent: 5751039 (1998-05-01), Kauffman et al.
patent: 5787457 (1998-07-01), Miller et al.
patent: 5808946 (1998-09-01), Roohparvar
patent: 5851876 (1998-12-01), Jenq
patent: 5867430 (1999-02-01), Chen et al.
patent: 5885866 (1999-03-01), Chen
patent: 5889727 (1999-03-01), Hsu et al.
patent: 5913928 (1999-06-01), Morzano
patent: 5936903 (1999-08-01), Jeng et al.
patent: 5956587 (1999-09-01), Chen et al.
patent: 5959887 (1999-09-01), Takashina et al.
patent: 5995438 (1999-11-01), Jeng et al.
patent: 6011751 (2000-01-01), Hirabayashi
patent: 6026465 (2000-02-01), Mills et al.
patent: 6077211 (2000-06-01), Vo
patent: 6081450 (2000-06-01), Nawaki
patent: 6081878 (2000-06-01), Estakhri et al.
patent: 6088264 (2000-07-01), Hazen et al.
patent: 6137133 (2000-10-01), Kauffman et al.
patent: 6141247 (2000-10-01), Roohparvar et al.
patent: 6240040 (2001-05-01), Akaogi et al.
patent: 6418506 (2002-07-01), Pashley et al.
patent: 08221312 (1996-08-01), None
Doyle: editor. Microsoft Press Computer Dictionary, 2nded., 1994, Microsoft Press, pp. 36,37 and 48.*
Keeth, et al., “DRAM circuit design: a tutorial,” IEEE Press, 2001, pp. 16-23, 142-153.
Micron Semiconductor Products, Inc., “2Mb, Smart 5 BIOS-Optimized Boot Block Flash Memory,”Flash Memorywww.micron.com, copyright 2000, Micron Technology, Inc., pp. 1-12.
Micron, “16 Mb: ×16 SDRAM”Synchronous DRAM, www.micron.com, copyright 1999 Micron Technology, Inc., pp. 1-51.

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