Power reduction mechanism for floating point register file...

Details Power reduction mechanism for floating point register file... Power reduction mechanism for floating point register file...

2005-08-23

2005-08-23

Tsai, Henry W. H. (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

Arithmetic operation instruction processing

C712S233000

Reexamination Certificate

active

06934831

ABSTRACT:
A system and method for reducing power consumed by a floating unit performing iterative calculations in a loop through selectively inhibiting floating point register file reads. One or more source register address values are compared with one or more current values generated from a first iteration of a loop, and upon determining that one ore or more values in the source registers are the same as one or more current generated values, floating point register file reads of the equal values from the one or more source registers are inhibited. The current generated values from the first iteration of the loop are preferably held in one or more pipeline registers.

REFERENCES:
patent: 5685009 (1997-11-01), Blomgren et al.
patent: 5974505 (1999-10-01), Kuttanna et al.
patent: 6009511 (1999-12-01), Lynch et al.

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