Familial correction with non-familial double bit error...

Details Familial correction with non-familial double bit error... Familial correction with non-familial double bit error...

2005-12-06

2005-12-06

Chase, Shelley A (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S785000

Reexamination Certificate

active

06973612

ABSTRACT:
Error correction and error detection related to DRAM chip failures, particularly adapted server memory subsystems. The application of a code for 128 bit memories is applied to a 20 bit directory store to improve reliability of the directory store memory of the computer system. The code uses ×4 bit DRAM devices organized in a code word of 20 data bit words and 12 check bits. These 12 check bits provide a code capable of 4 bit adjacent error correction within a family (i.e., in a ×4 DRAM) and double bit non-adjacent error detection across the entire 20 bit word, with single bit correction across the word as well. Each device can be though of as a separate family of bits, errors occurring in more than one family are not correctable, but may be detected if only one bit in each of two families is in error. Syndrome generation and regeneration are used together with a specific large code word. Decoding the syndrome and checking it against the regenerated syndrome yield data sufficient for providing the features described.

REFERENCES:
patent: 5490155 (1996-02-01), Abdoo et al.
patent: 5682394 (1997-10-01), Blake et al.
patent: 5757823 (1998-05-01), Chen et al.
patent: 6018817 (2000-01-01), Chen et al.
patent: 6453440 (2002-09-01), Cypher

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