Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2005-08-30
2005-08-30
Jackson, Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S315000, C257S316000, C257S318000, C257S413000
Reexamination Certificate
active
06936882
ABSTRACT:
A semiconductor device includes a substrate and an insulating layer formed on the substrate. A first device may be formed on the insulating layer. The first device may include a first fin formed on the insulating layer, a first dielectric layer formed on the first fin, and a partially silicided gate formed over a portion of the first fin and the first dielectric layer. A second device also may be formed on the insulating layer. The second device may include a second fin formed on the insulating layer, a second dielectric layer formed on the second fin, and a fully silicided gate formed over a portion of the second fin and the second dielectric layer.
REFERENCES:
patent: 4319395 (1982-03-01), Lund et al.
patent: 4399605 (1983-08-01), Dash et al.
patent: 6391750 (2002-05-01), Chen et al.
patent: 6451693 (2002-09-01), Woo et al.
patent: 6589836 (2003-07-01), Wang et al.
patent: 6657259 (2003-12-01), Fried et al.
patent: 6800905 (2004-10-01), Fried et al.
patent: 6846734 (2005-01-01), Amos et al.
patent: 2001/0045589 (2001-11-01), Takeda et al.
patent: 2002/0088971 (2002-07-01), Tezuka et al.
patent: 2004/0038464 (2004-02-01), Fried et al.
patent: 2004/0048424 (2004-03-01), Wu et al.
patent: 2004/0195628 (2004-10-01), Wu et al.
Digh Hisamoto et al., “FinFET—A Self-Aligned Double-Gate MOSFET Scalable to 20 nm,” IEEE Transactions on Electron Devices, vol. 47, No. 12, Dec. 2000, pp. 2320-2325.
Yang-Kyu Choi et al., “Sub-20nm CMOS FinFET Technologies,” 2001 IEEE, IEDM, pp. 421-424.
Xuejue Huang et al., “Sub-50 nm P-Channel FinFET,” IEEE Transactions on Electron Devices, vol. 48, No. 5, May 2001, pp. 880-886.
Xuejue Huang et al., “Sub 50-nm FinFET: PMOS,” 1999 IEEE, IEDM, pp. 67-70.
Yang-Kyu Choi et al., “Nanoscale CMOS Spacer FinFET for the Terabit Era,” IEEE Electron Device Letters, vol. 23, No. 1, Jan. 2002, pp. 25-27.
Co-pending U.S. Appl. No. 10/674,520 filed Oct. 2, 2003 entitled: “Damascene FinFET Gate With Selective Metal Interdiffusion,” 16 page specification, 19 sheets of drawings.
Copy of co-pending U.S. Appl. No. 10/857,931 filed Jun. 2, 2004, titled: “Selective Channel Implantation for Forming Semiconductor Devices with Different Threshold Values,” Haihong Wang et al., 21page specification, 20 sheets of drawings.
Ahmed Shibly S.
Wang Haihong
Yu Bin
Fenty Jesse A.
Harrity & Snyder LLP
Jackson Jerome
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