System and method for balancing capacitively coupled signal...

Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates

Reexamination Certificate

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C341S050000

Reexamination Certificate

active

06937067

ABSTRACT:
A signal balancing circuit for capacitively coupled signaling between transmitting and receiving devices over a plurality of capacitively coupled signal lines on which data signals are transmitted from the transmitting device to the receiving device. The signal balancing circuit includes an encode circuit for forcing a signal transition of a data signal for a data interval in response to the data signal maintaining the same logic state throughout a respective time interval. A balancing signal is generated having a logic level and a timing relative to the time intervals of the respective data signals indicative of inversion of a particular data signal. A decode circuit coupled to the encode circuit to receive the balancing signal forces a transition of the transitioned signal at the appropriate time in accordance with the balance signal to recover the original logic level of the data signal.

REFERENCES:
patent: 3782504 (1974-01-01), Billmaier et al.
patent: 4280221 (1981-07-01), Chun et al.
patent: 5124660 (1992-06-01), Cilingiroglu
patent: 5673130 (1997-09-01), Sundstrom et al.
patent: 5786979 (1998-07-01), Douglass
patent: 5818112 (1998-10-01), Weber et al.
patent: 5974464 (1999-10-01), Shin et al.
patent: 6087842 (2000-07-01), Parker et al.
patent: 6188232 (2001-02-01), Akram et al.
patent: 6242941 (2001-06-01), Vest et al.
patent: 6285201 (2001-09-01), Farnworth et al.
patent: 6310494 (2001-10-01), Ehben et al.
patent: 6357025 (2002-03-01), Tuttle
patent: 6368930 (2002-04-01), Enquist
patent: 6396292 (2002-05-01), Hembree et al.
patent: 6407566 (2002-06-01), Brunelle et al.
patent: 6425107 (2002-07-01), Caldara et al.
patent: 6490188 (2002-12-01), Nuxoll et al.
patent: 6496889 (2002-12-01), Perino et al.
patent: 6500696 (2002-12-01), Sutherland
patent: 6563133 (2003-05-01), Tong
patent: 6563299 (2003-05-01), Van Horn et al.
patent: 6620638 (2003-09-01), Farrar
patent: 6625073 (2003-09-01), Beffa
patent: 6690309 (2004-02-01), James et al.
patent: 6714031 (2004-03-01), Seki
patent: 6859883 (2005-02-01), Svestka et al.
patent: 2001/0039075 (2001-11-01), Doyle et al.
patent: 2001/0054908 (2001-12-01), Farnworth et al.
patent: 0 277 764 (1988-01-01), None
patent: 0366263 (1990-05-01), None
patent: 0 492 806 (1991-11-01), None
patent: 0 805 356 (1998-04-01), None
patent: 2 353 401 (2001-02-01), None
patent: 2 353 402 (2001-02-01), None
patent: WO 0215185 (2002-02-01), None
“International Technology Roadmap for Semiconductors”, Assembly and Packaging, 2001, pp. 1-21.
Karnezos, M. et al., “System in a Package (SiP) Benefits and Technical Issues”, inProceedings ofAPEX, San Diego, California, 2002, 7 pages.
Mick, S. et al., “4Gbps High-Density AC Coupled Interconnection”, Department of Electrical and Computer Engineering North Carolina State University, IEEE Custom Integrated Circuits Conference, May 12-16, 2002, pp. 133-140.
“Rapidly Advancing System-in-Package Fabrication Technology”, vol. 20, No.3, 2002, pp. 3-11.
Scanlan, C.M. et al., “System-In-Package Technology, Application and Trends”, 2001 Proceedings of SMTA International, Rosemont, Illinois, pp. 764-773.
Wang, M. et al., “Configurable Area-IO Memory for System-In-A-Package (SiP)”, 27thEuropean Solid-State Circuits Conference, Sep. 2001, 4 pages.

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