Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2005-08-30
2005-08-30
Tan, Vibol (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S086000, C326S126000, C326S115000, C326S127000, C327S108000
Reexamination Certificate
active
06937054
ABSTRACT:
Methods and structures are disclosed herein for programmably adjusting a peaking function of a differential signal receiver. The disclosed method includes inputting a pair of differential signals to a pair of input transistors coupled to conduct currents differentially between a pair of load impedances and a pair of tail transistors. The impedance of an adjustable shunt impedance element between the tail transistors of the receiver is varied by programming signal input, such that higher current is conducted over a peaking range of frequencies. In a disclosed structural embodiment, an integrated circuit is provided having a programmable peaking receiver. The programmable peaking receiver includes a pair of input transistors coupled to conduct differentially according to a pair of differential inputs applied to the pair of input transistors. Each of the input transistors produces an output in accordance with the differential input applied thereto. The programmable peaking receiver also includes a pair of tail transistors, coupled to draw current from the input transistors, and a programmably adjustable impedance element coupled between current-conducting nodes of the tail transistors. The impedance of the programmably adjustable impedance element is thereby adjustable in response to programming signal input to adjust a peaking function of the programmable peaking receiver.
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Hsu Louis L.
Selander Karl D.
Sorna Michael A.
Washburn William F.
Xu Huihao H.
International Business Machines - Corporation
Neff Daryl K.
Tan Vibol
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