Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2005-02-15
2005-02-15
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S201000
Reexamination Certificate
active
06856567
ABSTRACT:
A semiconductor device (such as a DRAM) includes a memory array that has dynamic memory cells. In a self refresh test mode, a self refresh test mode controller monitors and/or controls various blocks and internal signals in the semiconductor device. The self refresh test mode controller may communicate with a remote testing device through various conductors including one or more DQ lines and/or one or more address lines.
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Hur J. H.
TraskBritt
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