Method for testing an integrated semiconductor memory, and...

Details Method for testing an integrated semiconductor memory, and... Method for testing an integrated semiconductor memory, and...

2005-11-08

2005-11-08

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S233100, C365S185250

Reexamination Certificate

active

06963514

ABSTRACT:
An integrated semiconductor memory that can be tested includes a control circuit and a memory cell having a selection transistor. In a normal operating mode, the integrated semiconductor memory can be controlled by applying control signals and can be switched from a normal operating mode to a test operating mode by the applying a signal combination of the control signals. In the test operating mode, the control circuit interprets a first of the control signals as a signal for turning off the selection transistor and a second of the control signals or a signal combination of the control signals as a signal for switching the selection transistor into the on state. The method enables the testing of different times between reading a data set into the memory cell and turning off the selection transistor.

REFERENCES:
patent: 5184326 (1993-02-01), Hoffmann et al.
patent: 5689465 (1997-11-01), Sukegawa et al.
patent: 6385125 (2002-05-01), Ooishi et al.
Infineon Technologies AG, 128-Mbit Synchronous DRAM, Sep. 2001, pp. 1-52.

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